The integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) has experienced continuous rapid increase. For the most part, the improvement in integration density has come from repeated reductions in minimum feature size, allowing more components to be integrated into a given chip area.
The integration improvement is essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required. An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
Three-dimensional integrated circuits (3DICs) were thus formed, wherein dies may be stacked, with wire-bonding, flip-chip bonding, and/or through-silicon vias (TSV) used to connect the dies together and to connect the dies to package substrates. The conventional 3DICs, however, have a high form factor.